1. Field of the Invention
The present invention generally relates to a pixel array, and more particularly, to a pixel array with good display quality.
2. Description of Related Art
In recent years, the size of liquid crystal display (LCD) has been increased constantly. As a result, techniques for resolving the viewing angle problem in large-sized LCDs have been improved constantly. Multi-domain vertical alignment (MVA) LCD panel and advanced MVA (AMVA) LCD panel are two major wide viewing angle techniques among all LCD techniques. Since the AMVA LCD panel can effectively resolve the color washout problem in the MVA LCD panel, the AMVA LCD panel provides a better display quality compared to the MVA LCD panel.
FIG. 1 is an equivalent circuit diagram of a pixel array. FIG. 2 is a diagram of a single sub-pixel in FIG. 1. Referring to FIG. 1 and FIG. 2, the pixel array 200 includes a plurality of sub-pixels P2, and each of the sub-pixels P2 includes a first thin film transistor TFT1, a second thin film transistor TFT2, a third thin film transistor TFT3, a first pixel electrode ITO1 electrically connected to the first thin film transistor TFT1, and a second pixel electrode ITO2 electrically connected to the second thin film transistor TFT2. The first pixel electrode ITO1 is capacitively coupled to a common line COM1 on a TFT array substrate having the pixel array 200 to form a first storage capacitor Cs1, and the first pixel electrode ITO1 is capacitively coupled to a common electrode on an opposite substrate (for example, a color filter substrate) to form a first liquid crystal capacitor CLC1. Similarly, the second pixel electrode ITO2 is capacitively coupled to a common line COM2 on the TFT array substrate to form a second storage capacitor Cs2, and the second pixel electrode ITO2 is capacitively coupled to the common electrode on the opposite substrate (for example, a color filter substrate) to form a second liquid crystal capacitor CLC2.
As shown in FIG. 1 and FIG. 2, in the sub-pixel P2 electrically connected to the scan line SL(n−1), the gate or namely gate electrode of the first thin film transistor TFT1 and the gate or namely gate electrode of the second thin film transistor TFT2 are both electrically connected to the scan line SL(n−1), and the gate of the third thin film transistor TFT3 is electrically connected to the next scan line SL(n). Besides, the source or namely source electrode of the third thin film transistor TFT3 is electrically connected to the second pixel electrode ITO2, the drain or namely drain electrode D3 of the third thin film transistor TFT3 is capacitively coupled to the first pixel electrode ITO1 to form a first capacitor CcA, and the drain D3 of the third thin film transistor TFT3 is capacitively coupled to the common line COM1 under the first pixel electrode ITO1 to form a second capacitor CcB. When a high voltage is supplied to the scan line SL(n−1), image data can be recoded into the sub-pixel connected to the scan line SL(n−1) through the data lines DL(n−1) and DL(n). Herein, the first pixel electrode ITO1 and the second pixel electrode ITO2 have the same voltage level. When a high voltage is supplied to the scan line SL(n), the first capacitor CcA and the second capacitor CcB make the voltage of the first pixel electrode ITO1 different from the voltage of the second pixel electrode ITO2.
Because the drain of the second thin film transistor TFT2 extends across the first pixel electrode ITO1 and connected to the second pixel electrode ITO2, a parasitic capacitance Cx1 is generated between the drain D2 of the second thin film transistor TFT2 and the first pixel electrode ITO1. In addition, since the drain D3 of the third thin film transistor TFT3 extends across the second pixel electrode ITO2, a parasitic capacitance Cx2 is generated between the drain D3 of the third thin film transistor TFT3 and the second pixel electrode ITO2. The parasitic capacitances Cx1 and Cx2 reduce the voltage difference between the first pixel electrode ITO1 and the second pixel electrode ITO2. As a result, the problem of color washout cannot be effectively resolved. Thereby, the affection of the parasitic capacitances Cx1 and Cx2 in the sub-pixel P2 to the display quality has to be eliminated.